Current steering DACs receive digital input signals and produce positive and negative analog output currents based thereon. The positive and negative output currents are supplied from connections that are typically referred to as IOUT+ and IOUT−, and a differential voltage corresponding to the digital input signal is produced therebetween.
To facilitate current generation and steering functionality, current steering DACs include several parallel-connected unit cells, each of which includes a current source (typically including a transistor), cascode transistors, an amplifier, and switches. Each unit cell is controlled by a decoder that receives digital input signals that are to be converted to analog signals and produces drive signals that control the switches to produce the proper analog output current from the unit cell based on the digital input signals. The sum of the currents produced by the unit cells is the resulting overall analog current corresponding to the digital input signal.
An example, bias circuit 102 and unit cell 104 are shown in FIG. 1. A bias voltage, VBIAS, is provided to a buffer 106 that is coupled to the base of a transistor 108, which acts as a current source for the unit cell 104. The transistor 108 is coupled between a ground node 110 and a node 112 to which switches 114 and 116 are coupled. Cascode transistors 118, 120 are respectively coupled to the switches 114, 116. Currents are provided from the unit cell 104 by the cascode transistors 118, 120 at nodes IOUT+ and IOUT−. As shown in FIG. 1, various parasitic capacitances result between the inputs to the switches 114, 116 and the node 112. As a result, digital signals provided to the switch inputs are coupled to the node 112 via the parasitic capacitances. As such, when one or both of the inputs to the switches 114, 116 transitions from a logical one to a logical zero, this transient is conveyed to the node 112, which discharges the node 112 to a zero voltage and couples glitches to the gate of the transistor 108.
The unit cells in a DAC either all operate in a class A mode or all operate in a class B mode, based on the drive signals that control the switches in the unit cells. In the class A mode of operation, the drive signals controlling the switches are always complementary to each other, so that the current from the current source always goes to either IOUT+ or IOUT−. Thus, in the class A mode of operation, a constant current is drawn from the power supply, regardless of whether the output differential voltage is at zero or at its peak. For example, as shown in FIG. 2, digital signals provided to the DAC indicate that the DAC is to output a sinusoidal differential current signal 200, which can easily be converted to a differential voltage using a resistor. To that end, the decoder produces drive signals that are fed to switches in the unit cells. These switches controlled by the drive signals result in the output of complementary sinusoidal current signals on IOUT+ 202 and IOUT− 204 that range in amplitude between 0 amperes (A) and, for example, 0.04 A and that intersect at one-half amplitude (i.e., in FIG. 2 the signals 202 and 204 cross one another at 0.02 A and are 180 degrees out of phase with one another). Thus, the sum of the current signals 202 and 204 is constant at 0.04 A, as shown by the waveform at reference numeral 206. However, as shown by the current signal at reference numeral 200, the differential current created by the signals 202 and 204 is sinusoidal. To produce the currents shown in FIG. 2, the current sources and the cascode transistors of each unit cell are always ON and operate in correct bias voltage conditions. However, because the class A operating mode always consumes energy, even when a zero current differential is desired, the class A operating mode has the attribute of high current consumption.
An illustration of the class B operating mode is shown in FIG. 3. In general, the class B operating mode is one in which during the production of a positive output current the switches controlling IOUTP+ are turned ON proportionally to input signal amplitude, while the switches controlling IOUT− are all turned OFF. Conversely, for the production of a negative current, the switches controlling IOUT+ are turned OFF, while the switches controlling IOUT− are turned ON proportionally to the input signal. As shown in FIG. 3, a differential output signal 200 is produced by a differential between only positive half-cycle currents IOUT+ 302 and IOUT− 304. As described above, when the current IOUT+ is positive, the current IOUT− is 0; conversely, where the current IOUT− is positive, the current IOUT+ is 0. Thus, in the class B mode of operation, no switches are turned ON during the production of a zero differential output current. Accordingly, the current that is drawn from the current supply is proportional to the amplitude of the input signal, as shown at reference numeral 306. In the class B operating mode, the DAC has the lowest operating power for a given input signal.
While class B mode is efficient, in class B mode, when the current sources and cascodes are turned OFF completely and then turned ON, the transient glitches couple to sensitive bias nodes in the unit cells. As these bias nodes are usually driven by analog circuits having finite output impedance and parasitic or intentional capacitors, the disturbance in the bias voltages are carried forward to clock periods other than the one in which the glitches occurred. This leads to severe distortion in the output of the line driver/DAC.